32-bit RISC Architecture Two Instruction Sets:
– ARM High-performance 32-bit Instruction Set
– Thumb High-code-density 16-bit Instruction Set
Very Low Power Consumption: Industry-leader in MIPS/Watt
4G Bytes Linear Address Space
Von Neumann Load/Store Architecture:
– Single 32-bit Data Bus for Instructions and Data
3-Stage Pipeline Architecture:
– Fetch, Decode and Execute Stage
8-, 16-, and 32-bit Data Types
Single Cycle 32x8 Hardware Multiplier:
– Multiplication is Accelerated when Upper Bytes Are All Zero or One
On-chip JTAG Debug and In Circuit Emulation
Extensive Range of Third-party Application Development Tools
The ARM7TDMI embedded microcontroller core is a member of the Advanced RISC Machines (ARM) family of general purpose 32-bit microprocessors, which offer high performance and very lower power consumption. Its outstanding feature is the 16-bit Thumb subset of the most commonly used 32-bit instructions. These are expanded at run time with no degradation of system performance. This gives 16-bit code density (saving memory area and cost) coupled with 32-bit processor performance.
The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory.
The ARM memory interface has been designed to allow the performance potential to be realized without incurring high costs in the memory system. Speed-critical control signals are pipelined to allow system control functions to be implemented in standard low-power logic, and these control signals facilitate the exploitation of the fast local access modes offered by industry standard dynamic RAMs.
The ARM memory interface is also ideally suited to interfacing, either on-chip or offchip, with Atmel's Flash memory blocks. These give the benefits of in-system programmability and security, reducing time-to-market and system cost.
The ARM7TDMI core is supported by an extensive range of application development tools. These are fully described in the AT91Business Partners section of Atmels's Web site .